This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-066299, filed Mar. 12, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a package for, for example, a semiconductor device, and, more particularly, to a plastic package using a multilayer substrate.
FIG. 10 shows a conventional package for a semiconductor device, for example, a PPGA (Plastic Pin Grid Array) package. A semiconductor chip 102 is located at the center portion of a plastic package body (hereinafter called xe2x80x9cpackage bodyxe2x80x9d) 101 comprising a multilayer substrate. Formed on the package body 101 around the semiconductor chip 102 is a first interconnection pattern 103 to which, for example, a ground potential is supplied. Formed around the first interconnection pattern 103 is a second interconnection pattern 104 to which, for example, a power supply potential is supplied. A plurality of bonding pads 105 as signal input/output leads are laid around the second interconnection pattern 104, and a plurality of pads 106 are laid around those bonding pads 105. Those pads 106 are connected to the first and second interconnection patterns 103 and 104 and the bonding pads 105 by wires (not shown).
FIG. 11 is a cross-sectional view along the line 11xe2x80x9411 in FIG. 10. As shown in FIG. 11, the first and second interconnection patterns 103 and 104 are connected to a plurality of grounding bonding pads (not shown) and a power-supply bonding pad (not shown) by bonding wires 111 and 112. This connection of the first and second interconnection patterns 103 and 104 to the grounding bonding pads provided on the semiconductor chip 102 is made to supply a stable ground potential and power-supply potential to the semiconductor chip 102. The bonding pads 105 are connected by bonding wires 113 to signal bonding pads (not shown) that are laid around the semiconductor chip 102.
As apparent from FIGS. 10 and 11, the conventional package for a semiconductor device has the first and second interconnection patterns 103 and 104 and the plurality of pads 106 arranged concentrically around the semiconductor chip 102. The distances between the bonding pads of the semiconductor chip 102 and the first and second interconnection patterns 103 and 104 and the pads 106 naturally differ from one another. This necessitates that the bonding wires 111, 112 and 113 which respectively connect the first and second interconnection patterns 103 and 104 and the pads 106 to the bonding pads of the semiconductor chip 102 have different loops. That is, the conventional package for a semiconductor device requires three types of bonding loops be designed.
The conventional structure uses the three types of bonding wires 111, 112 and 113 of different lengths. If the number of bonding wires is increased, therefore, the bonding wires are likely to contact one another, producing defects.
Further, the use of multiple long bonding wires increases the resistance and inductance of the wires. This reduces the transfer speed for high-frequency signals and thus degrades the characteristics of the semiconductor chip 102.
Furthermore, as the first and second interconnection patterns 103 and 104 are laid out linearly around the semiconductor chip 102, the first and second interconnection patterns 103 and 104 do not have distinctive shapes. This leads to a lower precision of the position detection by the bonding machine at the time of wire-bonding the first and second interconnection patterns 103 and 104.
Accordingly, it is an object of the present invention to provide a package for a semiconductor device, which reduces the number of kinds of loop designs for bonding wires, prevent degradation of the electric characteristics and improve the alignment precision at the time of wire-bonding.
To achieve the above object, according to one aspect of this invention, there is provided a package for a semiconductor device comprising a substrate having a center portion on which a semiconductor chip is to be mounted; a first interconnection pattern formed on the substrate at a position around the semiconductor chip and having a continuous first interconnection main portion and a plurality of first projections protruding from the first interconnection main portion at approximately equal intervals; and a second interconnection pattern formed on the substrate at a position around the semiconductor chip and apart from the first interconnection pattern by a predetermined distance and having a continuous second interconnection main portion and a plurality of second projections so formed as to protrude from the second interconnection main portion at approximately equal intervals and to be engaged with the first projections of the first interconnection pattern in a non-contact manner.
The first and second projections of the first and second interconnection patterns are provided at approximately equal distances from a periphery of the semiconductor chip.
The base portions of the first and second projections of the first and second interconnection patterns may be rounded.
According to the second aspect of this invention, there is provided a package for a semiconductor device comprising a substrate having a center portion on which a semiconductor chip is to be mounted; a first interconnection pattern formed on the substrate at a position around the semiconductor chip and having a continuous first interconnection main portion and a plurality of first projections protruding from the first interconnection main portion at approximately equal intervals; a second interconnection pattern formed on the substrate at a position around the semiconductor chip and apart from the first interconnection pattern by a predetermined clearance and having a continuous second interconnection main portion and a plurality of second projections so formed as to protrude from the second interconnection main portion at approximately equal intervals and to be engaged with the first projections of the first interconnection pattern in a non-contact manner; and a third interconnection pattern laid between the first and second projections of the first and second interconnection patterns.
The first and second projections of the first and second interconnection patterns are provided at approximately equal distances from a periphery of the semiconductor chip.
The base portions of the first and second projections of the first and second interconnection patterns may be rounded.
According to the third aspect of this invention, there is provided a package for a semiconductor device comprising a substrate having a center portion on which a semiconductor chip is to be mounted; a first interconnection pattern formed on the substrate at a position around the semiconductor chip and having a continuous first interconnection main portion and a plurality of first projections protruding from the first interconnection main portion at approximately equal intervals; and a plurality of second interconnection patterns formed on the substrate at a position around the semiconductor chip and laid between the first projections of the first interconnection pattern.
The first projections of the first interconnection pattern and the second interconnection patterns are provided at approximately equal distances from a periphery of the semiconductor chip.
The base portions of the first projections of the first interconnection pattern may be rounded.
As described above, the present invention provides a package for a semiconductor device, which reduces the number of kinds of loop designs for bonding wires, prevent degradation of the electric characteristics and improve the alignment precision at the time of wire-bonding.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.